The present invention relates to an amplification type solid state imaging device output circuit provided with a source follower circuit.
There has conventionally been proposed an amplification type solid state imaging device whose pixels are each provided with an amplifying function, the device operating to read an amplified signal by means of a scanning circuit. In particular, there has been known an APS (Active Pixel Sensor) type image sensor having a CMOS type pixel construction advantageous to the integration thereof with a peripheral drive circuit and a signal processing circuit. According to this APS type image sensor, there are formed a photoelectric conversion section, an amplifying section, a pixel selecting section and a reset section within one pixel, and normally three to four MOS transistors are used in addition to the photoelectric conversion section constructed of a photodiode (PD).
FIG. 6 shows a circuit diagram of the essential part of an amplification type solid state imaging device in which each pixel is constructed of a PD and three transistors (Mabuchi et al., xe2x80x9cA xc2xc Inch 330k Pixel VGA CMOS Image Sensorxe2x80x9d, ITE Technical Report, IPU97-13, March, 1997). FIG. 6 shows a photodiode D1 that serves as a photoelectric conversion section, a MOS transistor Q11 that serves as an amplifying section, a MOS transistor Q12 that serves as a reset section, a MOS transistor Q13 that serves as a pixel selecting section, a pixel selecting clock line 11, a reset clock line 12, a vertical signal line 13 and a power line 14. Signal charges to be accumulated in the photodiode D1 are electrons, and each of the MOS transistors Q11, Q12, Q13, Q15, Q16, Q17 and Q30 is the n-channel type.
The MOS transistors Q12 and Q13 are driven by a first vertical scanning circuit 20 and a second vertical scanning circuit 21 via the pixel selecting clock line 11 and the reset clock line 12, respectively. The MOS transistor Q15 that serves as a constant current load is connected to the vertical signal line 13, and a signal on the vertical signal line 13 is conducted to a horizontal signal line 19 via the fourth MOS transistor Q16 for amplification use and the MOS transistor Q17 driven by a horizontal scanning circuit 22. The MOS transistor Q30 that serves as a constant current load is connected to the horizontal signal line 19, and a signal OS is outputted via an amplifier circuit 24. Fixed potentials VL1 and VL2 are applied to a gate of the MOS transistor Q15 and a gate of the MOS transistor Q30, respectively.
In FIG. 6, the pixels are all constructed of n-channel type MOS transistors and pn junction diodes, and therefore, the pixels can be formed through the normal CMOS processes. On the other hand, analog circuits such as the amplifier circuit 24 and digital circuits such as the vertical scanning circuits 20 and 21 and the horizontal scanning circuit 22 are generally constructed of CMOS circuits. Therefore, both the pixels and the peripheral circuits can be formed through common processes. This allows the power source to be commonized and practically a power voltage VD is used for the pixels and the peripheral circuits.
In order to reduce consumption of power in the amplification type solid state imaging device output circuit having the construction shown in FIG. 6, it is effective to lower the power voltage VD. According to the source follower circuit constructed of the MOS transistors Q11 and Q15, a photodiode potential is applied as an input vi to a gate of the MOS transistor Q11, and an output vo is obtained on the vertical signal line 13. FIG. 7 shows a relation between the input vi and the output vo of the above amplification type solid state imaging device output circuit. Assuming that the power voltage is VD, the gate voltage of the MOS transistor Q15 is VL and a threshold voltage of the MOS transistor Q15 is VTn, then the MOS transistor Q15 is required to operate in a saturation region (i.e., in a constant current operation region) in order that the input vi and the output vo have a linear relation, when the equation:
Vo greater than VLxe2x88x92VTnxe2x80x83xe2x80x83(1)
should hold.
In order to secure a sufficient operating margin when the power voltage VD is lowered, it is required to sufficiently reduce VLxe2x88x92VTn. For example, when the characteric curve changes from A to B as shown in FIG. 7, VLxe2x88x92VTn increases from VLAxe2x88x92VTn to VLBxe2x88x92VTn, consequently reducing the operating margin from Axe2x80x2 to Bxe2x80x2.
On the other hand, the MOS transistor Q11 inside the pixel has an ability gm to drive the vertical signal line 13, given by the following equation:
gm={square root over (2I0 xcexcCW/L+L )}xe2x80x83xe2x80x83(2)
where ID represents a drain current, xcexc represents mobility, C represents gate capacitance per unit area, W/L represents channel width/length of the MOS transistor Q11. Assuming that a signal line capacity is CL, then a time constant xcfx84 in the signal line driving stage is expressed by the following equation:
xcfx84=CL/gmxe2x80x83xe2x80x83(3)
Therefore, if the drain current ID is small, then gm is reduced. As a result, the time constant xcfx84 is increased, as a consequence of which the MOS transistor Q11 becomes unable to drive the vertical signal line 13 to vo within a given time.
The value ID of the constant current due to the MOS transistor Q15 is expressed from the relation of the saturation region by the following equation:
ID=(xcexcCW/2L)(VGxe2x88x92VT)2xe2x80x83xe2x80x83(4)
where VG represents a gate voltage and VT represents a threshold voltage.
With respect to VGxe2x88x92VT=VLxe2x88x92VTn, the drain current ID is shown in FIG. 8. In this case, the value of VLxe2x88x92VTn varies depending on variation in the gate voltage VL and the threshold voltage VTn.
As described in FIG. 7, it is necessary to set VLxe2x88x92VTn smaller in order to widen the operating margin. However, in the case that the width of variation xcex94VTn of VTn and the width of variation xcex94VL of VL are constant as shown in FIG. 8, there occurs a disadvantage that a ratio xcex94ID/ID0 of the variation xcex94ID of ID relative to the center value ID0 of ID increases as VLxe2x88x92VTn is set smaller.
As shown in FIG. 9, the gate voltage VL is generally obtained by dividing the power voltage VD by resistors R21 and R22. Therefore, the gate voltage VL varies according to variation in the power voltage VD. The threshold voltage VTn of the MOS transistor Q15 cannot normally avoid varying within a specified range during the MOS processes. In particular, VLxe2x88x92VTn is suppressed to a reduced value in connection with the equation (1), and therefore, the variation in the threshold voltage VTn strongly influences, as a consequence of which the drain current ID largely varies within the range of xcex94ID shown in FIG. 8. According to this source follower circuit, it is required to satisfy the equations (2) and (3) even with the minimum drain current ID from the point of view of the signal line driving ability, and the current value becomes very great at the maximum drain current ID, which is contradictory to the reduction in consumption of power.
In regard to the source follower circuit constructed of the fourth MOS transistor Q16 and the fifth MOS transistor Q30, the same argument can hold assuming that the power voltage is VD, the gate voltage of the MOS transistor Q30 is VL and the threshold voltage of the MOS transistor Q30 is VTn.
As a method for suppressing the variation in the threshold voltage of the MOS transistor located on the load side of the source follower circuit in view of the above reasons, there is proposed the one employing a monitor circuit (the prior art reference of Japanese Patent Laid-Open Publication No. SHO 60-58706) as shown in FIG. 10. This source follower circuit is provided with a diode D100, a transistor Q100 for resetting the diode D100, transistors Q101 through Q104 constituting an output circuit and transistors Q201 through Q204 that serve as a monitor circuit for applying a DC voltage to the gate of the transistor Q103. As shown in FIG. 11, a current flowing through the MOS transistor Q201 on the power source side of the monitor circuit greatly depends on the output voltage, and therefore, the current cannot be regarded as a constant current. As shown in FIG. 11, with respect to a variation in the threshold voltage of the MOS transistor, the output voltage of the MOS transistor Q203 located on the load side has a roughly constant value VBB at the intersection of the characteristic curves of the MOS transistor Q201 and the MOS transistor Q203, whereas the output current greatly varies as indicated by xcex94IBB. As is apparent from the equation (4), this means that VGxe2x88x92VT of the MOS transistor located on the load side greatly varies, indicating that this amplification type solid state imaging device output circuit is not appropriate for the reduction in voltage.
Accordingly, an object of the present invention is to provide an amplification type solid state imaging device output circuit capable of securing a sufficient operating margin with respect to fluctuations in a threshold voltage and a power voltage, suppressing fluctuations in consumption of current and stably operating at a low voltage, with a simple construction.
In order to achieve the aforementioned object, the present invention provides an amplification type solid state imaging device output circuit with a first source follower circuit comprised of a first MOS transistor that is formed on a semiconductor substrate and amplifies a photoelectric conversion signal from a photoelectric conversion element and a second MOS transistor used as a load that is formed on the semiconductor substrate and is connected to the first MOS transistor via a signal line, comprising: a third MOS transistor that is formed on the semiconductor substrate with a channel structure identical to that of the second MOS transistor and has a gate and a drain connected to a gate of the second MOS transistor so as to form a current mirror circuit with the second MOS transistor; and a first load that is formed on the semiconductor substrate and provided for flowing a roughly constant current through the third MOS transistor.
According to the above invention, if a roughly constant current flows through the third MOS transistor due to the first load in the second and third MOS transistors of an identical channel structure forming the current mirror circuit, then the gate voltage of the third MOS transistor is applied to the gate of the second MOS transistor used as a load, as a consequence of which a current roughly identical to the current flowing through the third MOS transistor flows through the second MOS transistor located on the load side. Therefore, the current flowing through the second MOS transistor located on the load side varies roughly in proportion to the variation in the current flowing through the third MOS transistor. The variation in the current flowing through the third MOS transistor is reduced with respect to the variation in the threshold voltage of the third MOS transistor by flowing a roughly constant current through the third MOS transistor of the current mirror circuit by means of the first load. With this arrangement, the variation in the current flowing through the second MOS transistor is reduced with respect to the variation in the threshold voltage of the second MOS transistor located on the load side. As described above, the variation in the current flowing through the second MOS transistor located on the load side is small in the first source follower circuit that amplifies the photoelectric conversion signal from the photoelectric conversion element and outputs the resulting signal to the signal line. Therefore, even if the potential difference between the gate voltage and the threshold voltage of the second MOS transistor located on the load side is reduced in order to widen the operating margin of the first source follower circuit, the ability to drive the signal line of the first source follower circuit scarcely changes. Therefore, a sufficient operating margin can be secured with respect to the fluctuation in the threshold voltage and the power voltage, and the fluctuation in consumption of current can be suppressed with a simple construction. By reducing the voltage difference between the gate voltage and the threshold voltage of the second MOS transistor located on the load side, a sufficient operating margin can be secured even if the power voltage is lowered.
In one embodiment of the invention, the first load is a MOS transistor of an opposite conductive type to a conductive type of the third MOS transistor, and a potential difference between the source and the gate of the MOS transistor is used as a power voltage.
According to the above embodiment, the first load of the third MOS transistor, i.e., the load of the current mirror circuit is provided by the MOS transistor which has the conductive type opposite to the conductive type of the third MOS transistor and in which the potential difference between the source and the gate is used as a power voltage. With this arrangement, the power voltage is sufficiently greater than the variation in threshold voltage of the MOS transistor. Therefore, the quantity of change in the voltage difference between the gate voltage and the threshold voltage is reduced, and the quantity of change in the current flowing through the third MOS transistor of the current mirror circuit is also reduced. Therefore, the quantity of change in the current flowing through the second MOS transistor located on the load side of the first source follower circuit for driving the signal line is reduced, allowing the operating margin of the first source follower circuit to be wider.
In one embodiment of the invention, the first load is a fixed resistor.
According to the above embodiment, the first load of the third MOS transistor, i.e., the load of the current mirror circuit is provided by a fixed resistance. With this arrangement, the quantity of change in the current flowing through the third MOS transistor of the current mirror circuit depending on the variation in the resistance value of the fixed resistor is reduced. Therefore, the quantity of change in the current flowing through the second MOS transistor located on the load side of the first source follower circuit for driving the signal line is also reduced, allowing the operating margin of the first source follower circuit to be wide.
In one embodiment of the invention, a potential difference between a gate voltage and a threshold voltage of the second MOS transistor is set to 1 V or less.
According to the above embodiment, the voltage difference between the gate voltage and the threshold voltage of the second MOS transistor located on the load side is set to 1 V or less. With this arrangement, the operating margin is widened, by which a sufficient operating margin can be secured even if the power voltage is lowered, allowing a low-voltage operation to be achieved. Therefore, an amplification type solid state imaging device capable of stably operating at a low voltage can be provided.
The present invention also provides an amplification type solid state imaging device output circuit provided with a first source follower circuit comprised of a first MOS transistor that is formed on a semiconductor substrate and amplifies a photoelectric conversion signal from a photoelectric conversion element and a second MOS transistor used as a load that is formed on the semiconductor substrate and is connected to the first MOS transistor via a signal line, comprising: a fourth MOS transistor that is formed on the semiconductor substrate and amplifies a signal on the signal line; a fifth MOS transistor used as a second load that is formed on the semiconductor substrate and is connected to the fourth MOS transistor via a common signal line so as to form a second source follower circuit with the fourth MOS transistor; a sixth MOS transistor that is formed on the semiconductor substrate with a channel structure identical to that of the fifth MOS transistor and has a gate and a drain connected to a gate of the fifth MOS transistor so as to form a current mirror circuit with the fifth MOS transistor; and a second load that is formed on the semiconductor substrate and provided for flowing a roughly constant current through the fifth MOS transistor.
According to the above prevention, similarly to the first source follower circuit, the variation in the current flowing through the fifth MOS transistor located on the load side is small in the second source follower circuit that amplifies the signal on the signal line and drives the common signal line. Therefore, even if the voltage difference between the gate voltage and the threshold voltage of the fifth MOS transistor located on the load side is reduced in order to widen the operating margin of this second source follower circuit, the ability of the second source follower circuit to drive the common signal line scarcely changes. Therefore, a sufficient operating margin can be secured and the fluctuation in consumption of current can be suppressed with respect to the fluctuation in the threshold voltage and the power voltage, with a simple construction. By reducing the voltage difference between the gate voltage and the threshold voltage of the fifth MOS transistor located on the load side, a sufficient operating margin can be secured even if the power voltage is lowered.